path: root/libs/wpewebkit/patches/138-JavaScriptCore-IPInt64-asm-RISCV64-port.patch

From d52c544b6421ac02bddf0c1896aaa3f71ab7ddce Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 23 Sep 2026 14:33:27 +0100
Subject: [PATCH] JavaScriptCore: port the IPInt 64-bit asm to RISCV64

InPlaceInterpreter64.asm restricts the dispatch-table base constants and
the argumINT dispatch to ARM64 and X86_64, and its atomic op macros raise
an offlineasm "error" on any other architecture, which aborts the build
rather than producing a runtime trap.

Add RISCV64 to the two pcrtoaddr-based dispatch sites, and turn the
unsupported-architecture "error" into "break" in the atomic macros so the
file assembles. The RISCV64 implementations of those atomics are supplied
separately.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
 .../llint/InPlaceInterpreter64.asm            | 211 +++++++++---------
 1 file changed, 109 insertions(+), 102 deletions(-)

--- a/Source/JavaScriptCore/llint/InPlaceInterpreter64.asm
+++ b/Source/JavaScriptCore/llint/InPlaceInterpreter64.asm
@@ -51,7 +51,7 @@ end
 
 # Dispatch target bases
 
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
 const ipint_dispatch_base = _ipint_unreachable
 end
 
@@ -76,8 +76,15 @@ elsif X86_64
     lshiftq (constexpr (WTF::fastLog2(JSC::IPInt::alignIPInt))), t0
     addq t1, t0
     jmp t0
+elsif RISCV64
+    # RISC-V: synthesize the ARM64 addlshift via lshiftp + addp, since the
+    # baseline rv64gc ISA does not have an add-with-shifted-operand form.
+    pcrtoaddr ipint_dispatch_base, t7
+    lshiftp (constexpr (WTF::fastLog2(JSC::IPInt::alignIPInt))), t0
+    addp t7, t0
+    jmp t0
 else
-    error
+    break
 end
 end
 
@@ -87,7 +94,7 @@ end
 macro pushQuad(reg)
     if ARM64 or ARM64E
         push reg, reg
-    elsif X86_64
+    elsif X86_64 or RISCV64
         push reg, reg
     else
         break
@@ -102,7 +109,7 @@ macro popQuad(reg)
     # FIXME: emit post-increment in offlineasm
     if ARM64 or ARM64E
         loadqinc [sp], reg, V128ISize
-    elsif X86_64
+    elsif X86_64 or RISCV64
         loadq [sp], reg
         addq V128ISize, sp
     else
@@ -208,7 +215,7 @@ macro argumINTDispatch()
     addp 1, MC
     bbgteq argumINTTmp, (constexpr IPInt::ArgumINTBytecode::NumOpcodes), _ipint_argument_dispatch_err
     lshiftp (constexpr (WTF::fastLog2(JSC::IPInt::alignArgumInt))), argumINTTmp
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     pcrtoaddr _argumINT_begin, argumINTDsp
     addp argumINTTmp, argumINTDsp
     jmp argumINTDsp
@@ -227,7 +234,7 @@ macro argumINTInitializeDefaultLocals()
 if ARM64 or ARM64E
     # offlineasm doesn't have xzr so emit it
     emit "stp x19, xzr, [x9]"
-elsif X86_64
+elsif X86_64 or RISCV64
     storep argumINTTmp, [argumINTDst]
     storep 0, 8[argumINTDst]
 end
@@ -508,7 +515,7 @@ end
     jmp .ipint_end_ret
 end)
 
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     const IPIntCallCallee = sc1
     const IPIntCallFunctionSlot = sc0
 elsif X86_64
@@ -1777,7 +1784,7 @@ ipintOp(_i32_div_s, macro()
     elsif ARM64 or ARM64E or RISCV64
         divis t1, t0
     else
-        error
+        break
     end
     pushInt32(t0)
     advancePC(1)
@@ -1796,7 +1803,7 @@ ipintOp(_i32_div_u, macro()
     elsif ARM64 or ARM64E or RISCV64
         divi t1, t0
     else
-        error
+        break
     end
     pushInt32(t0)
     advancePC(1)
@@ -1829,7 +1836,7 @@ ipintOp(_i32_rem_s, macro()
     elsif RISCV64
         remis t0, t1, t2
     else
-        error
+        break
     end
 
 .ipint_i32_rem_s_return:
@@ -1854,7 +1861,7 @@ ipintOp(_i32_rem_u, macro()
     elsif RISCV64
         remi t0, t1, t2
     else
-        error
+        break
     end
     pushInt32(t2)
     advancePC(1)
@@ -2034,7 +2041,7 @@ ipintOp(_i64_div_s, macro()
     elsif ARM64 or ARM64E or RISCV64
         divqs t1, t0
     else
-        error
+        break
     end
     pushInt64(t0)
     advancePC(1)
@@ -2053,7 +2060,7 @@ ipintOp(_i64_div_u, macro()
     elsif ARM64 or ARM64E or RISCV64
         divq t1, t0
     else
-        error
+        break
     end
     pushInt64(t0)
     advancePC(1)
@@ -2086,7 +2093,7 @@ ipintOp(_i64_rem_s, macro()
     elsif RISCV64
         remqs t0, t1, t2
     else
-        error
+        break
     end
 
 .ipint_i64_rem_s_return:
@@ -2111,7 +2118,7 @@ ipintOp(_i64_rem_u, macro()
     elsif RISCV64
         remq t0, t1, t2
     else
-        error
+        break
     end
     pushInt64(t2)
     advancePC(1)
@@ -9036,7 +9043,7 @@ macro doI32AtomicLoad(mem, dst)
     if ARM64 or ARM64E or X86_64
         atomicloadi [mem], dst
     else
-        error
+        break
     end
 end
 
@@ -9045,7 +9052,7 @@ macro doI64AtomicLoad(mem, dst)
     if ARM64 or ARM64E or X86_64
         atomicloadq [mem], dst
     else
-        error
+        break
     end
 end
 
@@ -9054,7 +9061,7 @@ macro doI32AtomicLoad8(mem, dst)
     if ARM64 or ARM64E or X86_64
         atomicloadb [mem], dst
     else
-        error
+        break
     end
 end
 
@@ -9063,7 +9070,7 @@ macro doI32AtomicLoad16(mem, dst)
     if ARM64 or ARM64E or X86_64
         atomicloadh [mem], dst
     else
-        error
+        break
     end
 end
 
@@ -9072,7 +9079,7 @@ macro doI64AtomicLoad8(mem, dst)
     if ARM64 or ARM64E or X86_64
         atomicloadb [mem], dst
     else
-        error
+        break
     end
 end
 
@@ -9081,7 +9088,7 @@ macro doI64AtomicLoad16(mem, dst)
     if ARM64 or ARM64E or X86_64
         atomicloadh [mem], dst
     else
-        error
+        break
     end
 end
 
@@ -9090,7 +9097,7 @@ macro doI64AtomicLoad32(mem, dst)
     if ARM64 or ARM64E or X86_64
         atomicloadi [mem], dst
     else
-        error
+        break
     end
 end
 
@@ -9106,7 +9113,7 @@ macro doI32AtomicStore(mem, val, memCopy
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9122,7 +9129,7 @@ macro doI64AtomicStore(mem, val, memCopy
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9138,7 +9145,7 @@ macro doI32AtomicStore8(mem, val, memCop
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9154,7 +9161,7 @@ macro doI32AtomicStore16(mem, val, memCo
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9170,7 +9177,7 @@ macro doI64AtomicStore8(mem, val, memCop
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9186,7 +9193,7 @@ macro doI64AtomicStore16(mem, val, memCo
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9202,7 +9209,7 @@ macro doI64AtomicStore32(mem, val, memCo
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9219,7 +9226,7 @@ macro doI32AtomicRmwAdd(mem, val, memCop
             addi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9236,7 +9243,7 @@ macro doI64AtomicRmwAdd(mem, val, memCop
             addq value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9254,7 +9261,7 @@ macro doI32AtomicRmwAdd8(mem, val, memCo
             addi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9272,7 +9279,7 @@ macro doI32AtomicRmwAdd16(mem, val, memC
             addi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9290,7 +9297,7 @@ macro doI64AtomicRmwAdd8(mem, val, memCo
             addi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9308,7 +9315,7 @@ macro doI64AtomicRmwAdd16(mem, val, memC
             addi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9326,7 +9333,7 @@ macro doI64AtomicRmwAdd32(mem, val, memC
             addi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9345,7 +9352,7 @@ macro doI32AtomicRmwSub(mem, val, memCop
             subi oldValue, value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9364,7 +9371,7 @@ macro doI64AtomicRmwSub(mem, val, memCop
             subq oldValue, value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9384,7 +9391,7 @@ macro doI32AtomicRmwSub8(mem, val, memCo
             subi oldValue, value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9404,7 +9411,7 @@ macro doI32AtomicRmwSub16(mem, val, memC
             subi oldValue, value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9424,7 +9431,7 @@ macro doI64AtomicRmwSub8(mem, val, memCo
             subi oldValue, value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9444,7 +9451,7 @@ macro doI64AtomicRmwSub16(mem, val, memC
             subi oldValue, value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9464,7 +9471,7 @@ macro doI64AtomicRmwSub32(mem, val, memC
             subi oldValue, value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9483,7 +9490,7 @@ macro doI32AtomicRmwAnd(mem, val, memCop
             andi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9502,7 +9509,7 @@ macro doI64AtomicRmwAnd(mem, val, memCop
             andq value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9521,7 +9528,7 @@ macro doI32AtomicRmwAnd8(mem, val, memCo
             andi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9540,7 +9547,7 @@ macro doI32AtomicRmwAnd16(mem, val, memC
             andi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9559,7 +9566,7 @@ macro doI64AtomicRmwAnd8(mem, val, memCo
             andi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9578,7 +9585,7 @@ macro doI64AtomicRmwAnd16(mem, val, memC
             andi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9597,7 +9604,7 @@ macro doI64AtomicRmwAnd32(mem, val, memC
             andi value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9615,7 +9622,7 @@ macro doI32AtomicRmwOr(mem, val, memCopy
             ori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9633,7 +9640,7 @@ macro doI64AtomicRmwOr(mem, val, memCopy
             orq value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9651,7 +9658,7 @@ macro doI32AtomicRmwOr8(mem, val, memCop
             ori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9669,7 +9676,7 @@ macro doI32AtomicRmwOr16(mem, val, memCo
             ori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9687,7 +9694,7 @@ macro doI64AtomicRmwOr8(mem, val, memCop
             ori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9705,7 +9712,7 @@ macro doI64AtomicRmwOr16(mem, val, memCo
             ori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9723,7 +9730,7 @@ macro doI64AtomicRmwOr32(mem, val, memCo
             ori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9741,7 +9748,7 @@ macro doI32AtomicRmwXor(mem, val, memCop
             xori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9759,7 +9766,7 @@ macro doI64AtomicRmwXor(mem, val, memCop
             xorq value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9777,7 +9784,7 @@ macro doI32AtomicRmwXor8(mem, val, memCo
             xori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9795,7 +9802,7 @@ macro doI32AtomicRmwXor16(mem, val, memC
             xori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9813,7 +9820,7 @@ macro doI64AtomicRmwXor8(mem, val, memCo
             xori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9831,7 +9838,7 @@ macro doI64AtomicRmwXor16(mem, val, memC
             xori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9849,7 +9856,7 @@ macro doI64AtomicRmwXor32(mem, val, memC
             xori value, oldValue, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9867,7 +9874,7 @@ macro doI32AtomicRmwXchg(mem, val, memCo
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9885,7 +9892,7 @@ macro doI64AtomicRmwXchg(mem, val, memCo
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9903,7 +9910,7 @@ macro doI32AtomicRmwXchg8(mem, val, memC
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9921,7 +9928,7 @@ macro doI32AtomicRmwXchg16(mem, val, mem
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9939,7 +9946,7 @@ macro doI64AtomicRmwXchg8(mem, val, memC
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9957,7 +9964,7 @@ macro doI64AtomicRmwXchg16(mem, val, mem
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9975,7 +9982,7 @@ macro doI64AtomicRmwXchg32(mem, val, mem
             move value, newValue
         end)
     else
-        error
+        break
     end
 end
 
@@ -9989,7 +9996,7 @@ macro doI32AtomicCmpxchg(mem, expected,
     elsif ARM64
         weakCASExchangeInt(memCopy, newVal, mem, scratch, expected)
     else
-        error
+        break
     end
 end
 
@@ -10002,7 +10009,7 @@ macro doI64AtomicCmpxchg(mem, expected,
     elsif ARM64
         weakCASExchangeQuad(memCopy, newVal, mem, scratch, expected)
     else
-        error
+        break
     end
 end
 
@@ -10016,7 +10023,7 @@ macro doI32AtomicCmpxchg8(mem, expected,
     elsif ARM64
         weakCASExchangeByte(memCopy, newVal, mem, scratch, expected)
     else
-        error
+        break
     end
 end
 
@@ -10030,7 +10037,7 @@ macro doI32AtomicCmpxchg16(mem, expected
     elsif ARM64
         weakCASExchangeHalf(memCopy, newVal, mem, scratch, expected)
     else
-        error
+        break
     end
 end
 
@@ -10044,7 +10051,7 @@ macro doI64AtomicCmpxchg8(mem, expected,
     elsif ARM64
         weakCASExchangeByte(memCopy, newVal, mem, scratch, expected)
     else
-        error
+        break
     end
 end
 
@@ -10058,7 +10065,7 @@ macro doI64AtomicCmpxchg16(mem, expected
     elsif ARM64
         weakCASExchangeHalf(memCopy, newVal, mem, scratch, expected)
     else
-        error
+        break
     end
 end
 
@@ -10072,7 +10079,7 @@ macro doI64AtomicCmpxchg32(mem, expected
     elsif ARM64
         weakCASExchangeInt(memCopy, newVal, mem, scratch, expected)
     else
-        error
+        break
     end
 end
 
@@ -10744,7 +10751,7 @@ macro weakCASExchangeByte(mem, value, ex
     .done:
         move scratch2, expected
     else
-        error
+        break
     end
 end
 
@@ -10764,7 +10771,7 @@ macro weakCASExchangeHalf(mem, value, ex
     .done:
         move scratch2, expected
     else
-        error
+        break
     end
 end
 
@@ -10784,7 +10791,7 @@ macro weakCASExchangeInt(mem, value, exp
     .done:
         move scratch2, expected
     else
-        error
+        break
     end
 end
 
@@ -10804,7 +10811,7 @@ macro weakCASExchangeQuad(mem, value, ex
     .done:
         move scratch2, expected
     else
-        error
+        break
     end
 end
 
@@ -12125,7 +12132,7 @@ mintAlign(_a1)
     mintArgDispatch()
 
 mintAlign(_a2)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     mintPop(a2)
     mintArgDispatch()
 else
@@ -12133,7 +12140,7 @@ else
 end
 
 mintAlign(_a3)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     mintPop(a3)
     mintArgDispatch()
 else
@@ -12141,7 +12148,7 @@ else
 end
 
 mintAlign(_a4)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     mintPop(a4)
     mintArgDispatch()
 else
@@ -12149,7 +12156,7 @@ else
 end
 
 mintAlign(_a5)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     mintPop(a5)
     mintArgDispatch()
 else
@@ -12157,7 +12164,7 @@ else
 end
 
 mintAlign(_a6)
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     mintPop(a6)
     mintArgDispatch()
 else
@@ -12165,7 +12172,7 @@ else
 end
 
 mintAlign(_a7)
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     mintPop(a7)
     mintArgDispatch()
 else
@@ -12359,7 +12366,7 @@ mintAlign(_r1)
     mintRetDispatch()
 
 mintAlign(_r2)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     subp StackValueSize, mintRetDst
     storeq wa2, [mintRetDst]
     mintRetDispatch()
@@ -12368,7 +12375,7 @@ else
 end
 
 mintAlign(_r3)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     subp StackValueSize, mintRetDst
     storeq wa3, [mintRetDst]
     mintRetDispatch()
@@ -12377,7 +12384,7 @@ else
 end
 
 mintAlign(_r4)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     subp StackValueSize, mintRetDst
     storeq wa4, [mintRetDst]
     mintRetDispatch()
@@ -12386,7 +12393,7 @@ else
 end
 
 mintAlign(_r5)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     subp StackValueSize, mintRetDst
     storeq wa5, [mintRetDst]
     mintRetDispatch()
@@ -12395,7 +12402,7 @@ else
 end
 
 mintAlign(_r6)
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     subp StackValueSize, mintRetDst
     storeq wa6, [mintRetDst]
     mintRetDispatch()
@@ -12404,7 +12411,7 @@ else
 end
 
 mintAlign(_r7)
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     subp StackValueSize, mintRetDst
     storeq wa7, [mintRetDst]
     mintRetDispatch()
@@ -12703,7 +12710,7 @@ uintAlign(_r5)
     uintDispatch()
 
 uintAlign(_r6)
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     popQuad(wa6)
     uintDispatch()
 else
@@ -12711,7 +12718,7 @@ else
 end
 
 uintAlign(_r7)
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     popQuad(wa7)
     uintDispatch()
 else
@@ -12792,7 +12799,7 @@ argumINTAlign(_a1)
     argumINTDispatch()
 
 argumINTAlign(_a2)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     storeq wa2, [argumINTDst]
     subp LocalSize, argumINTDst
     argumINTDispatch()
@@ -12802,7 +12809,7 @@ end
 
 
 argumINTAlign(_a3)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     storeq wa3, [argumINTDst]
     subp LocalSize, argumINTDst
     argumINTDispatch()
@@ -12811,7 +12818,7 @@ else
 end
 
 argumINTAlign(_a4)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     storeq wa4, [argumINTDst]
     subp LocalSize, argumINTDst
     argumINTDispatch()
@@ -12820,7 +12827,7 @@ else
 end
 
 argumINTAlign(_a5)
-if ARM64 or ARM64E or X86_64
+if ARM64 or ARM64E or X86_64 or RISCV64
     storeq wa5, [argumINTDst]
     subp LocalSize, argumINTDst
     argumINTDispatch()
@@ -12829,7 +12836,7 @@ else
 end
 
 argumINTAlign(_a6)
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     storeq wa6, [argumINTDst]
     subp LocalSize, argumINTDst
     argumINTDispatch()
@@ -12838,7 +12845,7 @@ else
 end
 
 argumINTAlign(_a7)
-if ARM64 or ARM64E
+if ARM64 or ARM64E or RISCV64
     storeq wa7, [argumINTDst]
     subp LocalSize, argumINTDst
     argumINTDispatch()